The present invention relates to a shared sense amplifier semiconductor memory device consisting of a dynamic random access memory which typically has storage elements or memory cells arranged in rows and columns to form a matrix. Each of the storage elements may comprise a MOS transistor and a storage capacitor.
A conventional semiconductor memory device of this type, such as that shown in Japanese Laid-Open Patent Application No. 82286/1982, comprises at least two arrays (a right array, and a left array), each having folded bit lines extending parallel with each other. Flip-flop sense amplifiers are arranged in a row between the arrays and are shared between the arrays. That is, each sense amplifier has a pair of sense nodes connected to a respective one of bit-line pairs of each of the two arrays through transfer transistors. There is a provision that the two arrays are not selected simultaneously. Sharing the sense amplifiers reduces the total number of sense amplifiers, and hence the chip area can be reduced. Moreover, because of the shorter bit lines, the sensitivity of the sense amplifier is effectively increased. However, the prior art memory device has a limitation in that an irreducible minimum amount of power is dissipated; this amount of wasted power cannot be made small enough for certain applications. This power loss is due to charging and discharging currents which flow through the bit lines of the array of the unselected side during the refresh cycle.